XC2S200-5PQ208C

Product Summary

The XC2S200-5PQ208C is a Field-Programmable Gate Array. It gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S200-5PQ208C offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200 MHz. Spartan-IIE devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined architecture based on the proven Virtex-E platform. Features include block RAM, distributed RAM, 16 selectable I/O standards, and four DLLs(Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.

Parametrics

XC2S200-5PQ208C absolute maximum ratings: (1)VCCINT Supply voltage relative to GND: –0.5 to 3.0V; (2)VCCO Supply voltage relative to GND: –0.5 to 4.0V; (3)VREF Input reference voltage: –0.5 to 3.6V; (4)VIN Input voltage relative to GND: –0.5 to 5.5V; (5)VTS Voltage applied to 3-state output: –0.5 to 5.5V; (6)TSTG Storage temperature (ambient): –65 to +150℃; (7)TJ Junction temperature: +125℃.

Features

XC2S200-5PQ208C features: (1)Second generation ASIC replacement technology; (2)16 bits/LUT distributed RAM; (3)Configurable 4K-bit true dual-port block RAM; (4)Fast interfaces to external RAM; (5)Fully PCI compliant; (6)Low-power segmented routing architecture; (7)Full readback ability for verification/observability; (8)Dedicated carry logic for high-speed arithmetic; (9)Efficient multiplier support; (10)Cascade chain for wide-input functions; (11)Abundant registers/latches with enable, set, reset; (12)Four dedicated DLLs for advanced clock control; (13)Four primary low-skew global clock distribution nets; (14)IEEE 1149.1 compatible boundary scan logic; (15)Low cost packages available in all densities; (16)Family footprint compatibility in common packages; (17)16 high-performance interface standards, including LVDS and LVPECL; (18)Hot swap Compact PCI friendly; (19)Zero hold time simplifies system timing Fully supported by powerful Xilinx ISE development system.

Diagrams