XC4006E-3PQ160C

Field Programmable Gate Array, QFP44, XC4006E-3PQ160C, Xilinx

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PartNumber:: XC4006E-3PQ160C

Brand:: Xilinx, Inc - Xilinx | Pack: QFP | D/C: 11+

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Products Upload time: 2012-03-22

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Product Summary

The XC4006E-3PQ160C is a high-performance, high-capacity Field Programmable Gate Array (FPGA) provided the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, the XC4006E-3PQ160C combines architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs.

Parametrics

XC4006E-3PQ160C specifications: (1)Gate Capacity=8000; (2)Configurable Logic Blocks=256; (3)Number of User I/Os=128; (4)Program Data (Bits)=119792; (5)Logic Level Family=CMOS and T; (6)Maximum Toggle Rate=125M; (7)V(OL)Max.(V)Lo Level Out.Volt.=0.4; (8)@Iol (A)=12m; (9)V(OH)Min.(V)Hi Level Out.Volt.=2.4; (10)@IOH (test)=4.0m; (11)VIH Min. (TTL) (V)=2.0; (12)VIL Max. (TTL) (V)=0.8; (13)VIH Min. (CMOS) (V)=3.5; (14)VIL Max. (CMOS) (V)=1.0; (15)Vsup (+) Maximum (V)=7.5; (16)Digital Input V Max (V)=7.5; (17)Vsup(+) Nom.(V) Pos.Sup.Volt.=5.0; (18)Quiescent Current Max (TTL)=3m; (19)Package Body Material=Plastic; (20)Package=QFP; (21)Pins=160; (22)Military=N; (23)Technology=CMOS.

Features

XC4006E-3PQ160C features: (1)Select-RAMTM memory: on-chip ultra-fast RAM with synchronous write option; (2)dual-port RAM option; (3)Fully PCI compliant (speed grades -2 and faster); (4)Abundant flip-flops; (5)Flexible function generators; (6)Dedicated high-speed carry logic; (7)Wide edge decoders on each edge; (8)Hierarchy of interconnect lines; (9)Internal 3-state bus capability; (10)Eight global low-skew clock or signal distribution networks; (11)System Performance beyond 80 MHz; (12)Flexible Array Architecture; (13)Low Power Segmented Routing Architecture.