XC95108-7TQ100I

CPLD, PLCC84, -0.5 to 7.0 V, XC95108-7TQ100I, Xilinx

Rated 5 Rating 5 | reviews | Write a review

Price:: US $43.00~46.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $43.00~46.00

PartNumber:: XC95108-7TQ100I

Brand:: Xilinx, Inc - Xilinx | Pack: QFP | D/C: 11+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. lucky's store

(Hong Kong)

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2012-03-22

From Other Seller

Part Number:XC95108-7TQ100I
US $43.00 - 46.00
AT25256AW-10SU-2.7

US $0.65 - 1.50 / Piece
(0) Remove
IRFP260N

US $1.30 - 4.20 / Piece
(0) Remove
Quantity:

piece

Product Summary

The XC95108-7TQ100I is a CPLD. The XC95108-7PQ160I provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members.

Parametrics

XC95108-7TQ100I absolute maximum ratings: (1)VCC Supply voltage relative to GND: -0.5 to 7.0 V; (2)VIN DC input voltage relative to GND: -0.5 to VCC + 0.5 V; (3)VTS Voltage applied to 3-state output with respect to GND: -0.5 to VCC + 0.5 V; (4)TSTG Storage temperature: -65 to +150℃; (5)TSOL Max soldering temperature (10 s @ 1/16 in = 1.5 mm): +260℃.

Features

XC95108-7TQ100I features: (1)High-performance: 5 ns pin-to-pin logic delays on all pins; fCNT to 125 MHz; (2)Large density range: 36 to 288 macrocells with 800 to 6,400 usable gates; (3)5V in-system programmable: Endurance of 10,000 program/erase cycles; Program/erase over full commercial voltage and ; (4)temperature range; (5)Enhanced pin-locking architecture; (6)Flexible 36V18 Function Block: 90 product terms drive any or all of 18 macrocells within Function Block; (7)Global and product term clocks, output enables, set and reset signals; (8)Extensive IEEE Std 1149.1 boundary-scan (JTAG) support; (9)Programmable power reduction mode in each macrocell; (10)Slew rate control on individual outputs; (11)User programmable ground pin capability; (12)Extended pattern security features for design protection; (13)Advanced CMOS 5V FastFLASH technology; (14)Supports parallel programming of multiple XC9500 devices.